This invention relates to a dynamic random access memory(DRAM) cell, and more particularly to a DRAM cell having no a capacitor using a silicon-on-insulator (SOI) substrate.
FIG. 1a shows a sectional view of a conventional DRAM cell and FIG. 1b shows an equivalent circuit of the DRAM cell in FIG. 1a. The reference numeral 101 denotes an isolation film, 102 a gate electrode(word line) of a transistor Q, 103 a bit line, 104 a storage electrode of a capacitor C, 105 a dielectric of the capacitor C, 106 a plate electrode of the capacitor C, 107 an intermediate insulating layer, 109 a silicon substrate, and 110 and 111 a source and a drain regions of the transistor Q. As shown in FIG. 1a and FIG. 1b, an electrically readable and programmable DRAM cell includes one transistor Q and one capacitor C. In program, the signal xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is programmed in the capacitor C according to the charge of electrons. In read, the signal xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d programmed in the capacitor C is read through the transistor Q.
In order to increase the integrity of DRAM, it should reduce the transistor Q as well as the capacitor C in size. The capacitance of the capacitor C depends on the size of the capacitor. The capacitance of the capacitor C is decreased with reduction of the size and therefore it can not reduce in size infinitely. In order to assuredly program the signal xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in the capacitor C and to accurately read the signal xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d programmed in the capacitor C, the capacitor C should have the capacitance of above 20 fF(femto-farad). The reason is that it is for charges accumulated in the capacitor C to directly use in driving a sense amplifier.
In more detail, in program, the signal xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is programmed in the capacitor C by turning on the transistor Q. In read, the charges charged in the capacitor C is discharged through the transistor by turning on the transistor Q and the discharged charges are transferred to an external sense amplifier(not shown in drawings) connected to the bit line 103 through the bit line 103. At this time, the voltage variation of the sense amplifier is produced according to an amount of the transferred charges to read the signal programmed in the capacitor C.
Because a parasitic capacitor is made in the bit line, while charges discharged from the capacitor are transferred to the sense amplifier, a portion of the charges becomes extinct. In consideration of extinction of charges through the parasitic capacitor in the bit line, the capacitor having a capacitance of beyond a selected capacity, for example above 20 fF should be required in the DRAM cell. Furthermore, in case the capacitor has a relatively low capacitance, it takes a lot of time to reach charges from the capacitor to a sense amplifier, resulting in a lowering of operation speed of the DRAM cell. So as to solve the problem, the capacitor having a capacitance of beyond a selected capacity, for example above 20 fF should be required. Therefore, so as to increase the integrity of DRAM, it is very essential to reduce the size of the capacitor with maintenance of the desired capacitance. Recently, the study on the capacitor with small size and a large capacitance is in progress. For an example, the formation technology of a 3-dimensional capacitor is proposed to enlarge an effective area of a capacitor in a relatively small chip size. However, the process for fabricating the 3-dimensional capacitor is very complicate and difficult, thereby resulting in increase in fabrication cost of DRAM cells and decrease in fabrication yield.
There is an object of the present invention to provide a DRAM cell having no capacitance using a SOI substrate and a method for fabricating the same.
According to an aspect of the present invention, there is provided to a DRAM cell, comprising: a silicon layer doped with impurities of a first conductivity type; a MOS transistor having a gate formed on one surface of a semiconductor layer and a source and drain regions formed in the semiconductor layer under the gate, the source and drain regions being doped with a first conductivity impurity to induce a channel in the semiconductor layer; an insulating layer formed on another surface of the semiconductor layer; a plate electrode formed on the insulating layer; and a purge region formed in the semiconductor layer so as to purge minor carriers induced at an interface between the semiconductor layer and the insulating layer, the purge region being doped with a second conductivity impurity.
According to another aspect of the present invention, there is provided to a DRAM cell, comprising: a silicon-on-insulator (SOI) substrate where an insulating layer is sandwitched between a first silicon layer and a second silicon layer doped with impurities of a first conductivity type; a metal oxide silicon (MOS) transistor having a gate formed on the second silicon layer and a source and drain regions formed in the second silicon layer, the source and drain regions being doped with impurities of a second conductivity type to induce a channel in the second silicon layer under the gate; a plate junction region formed in the first silicon layer, the plate junction region being doped with impurities of the second conductivity type; and a purge region formed in the second silicon layer to purge minor carriers induced in an interface surface between the second silicon layer and the insulating layer, the purge region doped with impurities of the first conductivity type.
According to further another aspect of the present invention, there is provided to a DRAM, comprising: a silicon layer doped with impurities of a first conductivity type; a metal oxide semiconductor (MOS) transistor having a gate formed on one surface of the silicon layer and a source and drain regions formed in the silicon layer, the source and drain regions being doped with impurities of a second conductivity type to induce a channel in the silicon layer under the gate; an insulating layer formed on another surface of the silicon layer; a plate electrode formed on the insulating layer; a purge region formed in the silicon layer to purge minor carriers induced at a back surface of the silicon layer which is an interface surface between the silicon layer and the insulating layer, the purge region being doped with impurities of the first conductivity type; a word line connected to the gate of the MOS transistor, the word line for driving the MOS transistor; and a bit line connected to the drain region of the MOS transistor, the bit line for receiving and providing a binary data;
wherein the binary data is programmed in the DRAM according to whether the minor carriers are induced at the back surface or not and the binary data is read from the DRAM through the bit line by sensing the substrate current flowing through the MOS transistor.
According to still another aspect of the present invention, there is provided to a method for fabricating a DRAM cell, comprising the steps of: sequentially forming an oxide film and a doped polysilicon layer on a first silicon layer having a first conductivity type; patterning the polysilicon layer to form a plate electrode; forming an insulating layer on the first silicon layer including the plate electrode; bonding a second silicon substrate to the insulating layer; removing the first silicon layer by a selected thickness through a chemical mechanical polishing process to form a thin silicon layer; forming an isolation film in the silicon layer to define an active region; forming a gate on the active region of the silicon layer and a source and a drain regions in the silicon layer by doping impurities of a second conductivity type in the silicon layer so as to induce a channel in the silicon layer, thereby forming a metal oxide semiconductor transistor; and forming a purge region by doping impurities of the first conductivity type in the silicon layer.
According to still another aspect of the present invention, there is provided to a method for fabricating a DRAM cell, comprising the steps of: preparing a silicon-on insulator (SOI) substrate where an insulating layer is sandwitched between a first silicon layer having a first conductivity type and a second silicon layer; forming a plate region having a second conductivity type in the first silicon layer at an interface of the insulating layer and the first silicon layer; forming an isolation film in the silicon layer to define an active region; forming a gate on the active region of the silicon layer and a source and a drain regions in the silicon layer by doping impurities of the second conductivity type in the silicon layer so as to induce a channel in the silicon layer, thereby forming a metal oxide semiconductor transistor; and forming a purge region by doping impurities of the first conductivity type in the silicon layer.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.